On-Line Error Detecting Constant Delay Adder

نویسندگان

  • Whitney J. Townsend
  • Jacob A. Abraham
  • Parag K. Lala
چکیده

Fault tolerance requires the inclusion of redundant information. In this paper an on-line error detecting adder is presented in which the redundant information serves a dual purpose. It provides fault tolerance during the arithmetic operations while also providing a method by which addition is constrained to become a constant delay operation regardless of the word size of the operands.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Imprecise Minority-Based Full Adder for ‎Approximate Computing Using CNFETs

   Nowadays, the portable multimedia electronic devices, which employ signal-processing modules, require power aware structures more than ever. For the applications associating with human senses, approximate arithmetic circuits can be considered to improve performance and power efficiency. On the other hand, scaling has led to some limitations in performance of nanoscale circuits. According...

متن کامل

Implementation of Error Detection Network in High- Speed Variable Latency Speculative Han-Carlson Adder

Variable latency adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. Kogge-Stone adder consists of large number of black cells and many wire tracks. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct...

متن کامل

Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplier

Problem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multip...

متن کامل

Constant Delay Linear Size Adder under Left-to-Right Input Arrival

A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...

متن کامل

Fast Mux-based Adder with Low Delay and Low PDP

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2003